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| COTS PEM Austin Semiconductor, Inc. AS5SP1M18DQ SSRAM 18Mb, 1M x 18, Synchronous SRAM Pipeline Burst, Single Cycle Deselect NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 98 97 96 95 92 91 89 87 84 99 94 93 90 88 86 85 83 100 82 81 A A CE1\ CE2 NC NC BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A Plastic Encapsulated Microcircuit 80 79 78 77 76 75 74 73 72 71 70 69 68 67 Features * * * * * * * * * * * * * * * * * Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter (base +3) for Burst operations Self-Timed Write Cycles On-Chip Address and Control Registers Byte Write support Global Write support On-Chip low power mode [powerdown] via ZZ pin Interleaved or Linear Burst support via Mode pin Three Chip Enables for ease of depth expansion without Data Contention. Two Cycle load, Single Cycle Deselect Asynchronous Output Enable (OE\) Three Pin Burst Control (ADSP\, ADSC\, ADV\) 3.3V Core Power Supply 3.3V/2.5V IO Power Supply JEDEC Standard 100 pin TQFP Package, MS026-D/BHA Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQPb NC VSSQ VDDQ NC NC NC A NC NC VDDQ VSSQ NC DQPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC SSRAM [SPB] 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 MODE A A A A A1 A0 NC* NC* VSS Fast Access Times Parameter Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 Units ns ns ns Block Diagram OE\ ZZ CLK CE1\ CE2 CE3\ BWE\ BWx\ GW\ ADV ADSC\ ADSP\ MODE A0-Ax BURST CNTL. Address Registers Row Decode Column Decode CONTROL BLOCK General Description ASI's AS5SP1M18DQ is a 18Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 1M x 18. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. ASI's AS5SP1M18DQ includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are handled by three (3) input pins, ADV, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Status Processor (ADSP\) or Address Status Cache controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system's burst sequence control block and are controlled by Address Advance (ADV) control input. I/O Gating and Control Memory Array x18 SBP Synchronous Pipeline Burst Two (2) cycle load One (1) cycle de-select One (1) cycle latency on Mode change Output Register Output Driver DQx, DQPx Input Register AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 1 VDD A A A A A A A A A 50 COTS PEM Austin Semiconductor, Inc. Pin Description/Assignment Table Signal Name Clock Address Address Symbol CLK A0, A1 A Type Input Input Input(s) Pin Description This input registers the address, data, enables, Global and Byte writes as well as the burst control functions 37, 36 Low order, Synchronous Address Inputs and Burst counter address inputs 35, 34, 33, 32, 31, 100, Synchronous Address Inputs 99, 82, 81, 42, 44, 45, 46, 47, 48, 49, 50, 43,83 98, 92 Active Low True Chip Enables 97 Active High True Chip Enable 88 Active Low True Global Write enable. Write to all bits 93, 94 Active Low True Byte Write enables. Write to byte segments 89 Active Low True Byte Write Function enable Active Low True Asynchronous Output enable Address Strobe from Controller. When asserted LOW, Address is captured in the address registers and A0-A1 are loaded into the Burst When ADSP\ and ADSC are both asserted, only ADSP is recognized 84 Synchronous Address Strobe from Processor. When asserted LOW, Address is captured in the Address registers, A0-A1 is registered in the burst counter. When both ADSP\ and ADSC\ or both asserted, only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH 83 Advance input Address. When asserted HIGH, address in burst counter is incremented. 64 Asynchronous, non-time critical Power-down Input control. Places the chip into an ultra low power mode, with data preserved. 74,24 Bidirectional I/O Parity lines. As inputs they reach the memory array via an input register, the address stored in the register on the rising edge of clock. As and output, the line delivers the valid data stored in the array via an output register and output driver. The data delieverd is from the previous clock period of the READ cycle. 58, 59, 62, 63, 68, 69, Bidirectional I/O Data lines. As inputs they reach the memory 72, 73, 8, 9, 12, 13, 18, array via an input register, the address stored in the register on the 19, 22, 23 rising edge of clock. As and output, the line delivers the valid data stored in the array via an output register and output driver. The data delieverd is from the previous clock period of the READ cycle. 31 Interleaved or Linear Burst mode control 91, 15, 41, 65 Core Power Supply 90, 17, 40, 67 Core Power Supply Ground 4, 11, 20, 27, 54, 61, Isolated Input/Output Buffer Supply 70, 77 5, 10, 21, 26, 55, 60, Isolated Input/Output Buffer Ground 71, 76 1, 2, 3, 6, 7, 14, 16, 25, No connections to internal silicon 28, 29, 30, 38, 39, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 87 86 85 AS5SP1M18DQ SSRAM Chip Enable Chip Enable Global Write Enable Byte Enables Byte Write Enable Output Enable Address Strobe Controller CE1\, CE3\ CE2 GW\ BWa\, BWb\ BWE\ OE\ ADSC\ Input Input Input Input Input Input Input Address Strobe from Processor ADSP\ Input Address Advance Power-Down Data Parity Input/Outputs ADV ZZ DQPa, DQPb Input Input Input/ Output Data Input/Outputs DQa, DQb, DQc Input/ DQd Output Burst Mode Power Supply [Core] Ground [Core] Power Supply I/O I/O Ground No Connection(s) MODE VDD VSS VDDQ VSSQ NC Input Supply Supply Supply Supply NA Logic Block Diagram A0, A1, Ax MODE ADV\ CLK ADDRESS REGISTER 2 A0, A1 Burst CounterQ1 and CLR Logic Q0 ADSC\ ADSP\ BWb\ Byte Write Register DQb, DQPb Byte Write Driver DQb, DQPb Memory Array Sense Amps Output Registers Output Buffers DQx, DQPx BWa\ BWE\ GW\ CE1\ CE2 CE3\ OE\ Byte Write Register DQa, DQPa Enable Register Pipeline Enable Byte Write Driver DQa, DQPa Input Registers ZZ Sleep Control AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 2 COTS PEM Austin Semiconductor, Inc. Functional Description AS5SP1M18DQ SSRAM cycle READS are supported. Once the READ operation has been completed and deselected by use of the Chip Enable(s) and either Austin Semiconductor's AS5SP1M18DQ Synchronous SRAM is ADSP\ or ADSC\, its outputs will tri-state immediately. manufactured to support today's High Performance platforms utilizing the Industries leading Processor elements including those A Single ADSP\ controlled WRITE operation is initiated when of Intel and Motorola. The AS5SP1M18DQ supports both of the following conditions are satisfied at the time of Clock Synchronous SRAM READ and WRITE operations as well as (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip Synchronous Burst READ/WRITE operations. All inputs with Enable(s) are asserted ACTIVE. The address presented to the the exception of OE\, MODE and ZZ are synchronous in nature address bus is registered and loaded on CLK HIGH, then and sampled and registered on the rising edge of the devices input presented to the core array. The WRITE controls Global Write, clock (CLK). The type, start and the duration of Burst Mode and Byte Write Enable (GW\, BWE\) as well as the individual operations is controlled by MODE, ADSC\, ADSP\ and ADV as Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are well as the Chip Enable pins CE1\, CE2, and CE3\. All ignored on the first machine cycle. ADSP\ triggered WRITE synchronous accesses including the Burst accesses are enabled via accesses require two (2) machine cycles to complete. If Global the use of the multiple enable pins and wait state insertion is Write is asserted LOW on the second Clock (CLK) rise, the data supported and controlled via the use of the Advance control presented to the array via the Data bus will be written into the array at the corresponding address location specified by the (ADV). Address bus. If GW\ is HIGH (inactive) then BWE\ and one or The ASI AS5SP1M18DQ supports both Interleaved as well as more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\) Linear Burst modes therefore making it an architectural fit for controls the write operation. All WRITES that are initiated in this either the Intel or Motorola CISC processor elements available on device are internally self timed. the Market today. A Single ADSC\ controlled WRITE operation is initiated when The AS5SP1M18DQ supports Byte WRITE operations and enters the following conditions are satisfied: [1] ADSC\ is asserted this functional mode with the Byte Write Enable (BWE\) and the LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). Global asserted (TRUE or Active), and [4] the appropriate combination Writes are supported via the Global Write Enable (GW\) and of the WRITE inputs (GW\, BWE\, BWx\) are asserted Global Write Enable will override the Byte Write inputs and will (ACTIVE). Thus completing the WRITE to the desired Byte(s) or the complete data-path. ADSC\ triggered WRITE accesses perform a Write to all Data I/Os. require a single clock (CLK) machine cycle to complete. The The AS5SP1M18DQ provides ease of producing very dense address presented to the input Address bus pins at time of clock arrays via the multiple Chip Enable input pins and Tri-state HIGH will be the location that the WRITE occurs. The ADV pin is ignored during this cycle, and the data WRITTEN to the array outputs. will either be a BYTE WRITE or a GLOBAL WRITE depending on the use of the WRITE control functions GW\ and BWE\ as Single Cycle Access Operations well as the individual BYTE CONTOLS (BWx\). A Single READ operation is initiated when all of the following conditions are satisfied at the time of Clock (CLK) HIGH: [1] Deep Power-Down Mode (SLEEP) ADSP\ pr ADSC\ is asserted LOW, [2] Chip Enables are all asserted active, and [3] the WRITE signals (GW\, BWE\) are in The AS5SP1M18DQ has a Deep Power-Down mode and is their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH. controlled by the ZZ pin. The ZZ pin is an Asynchronous input The address presented to the Address inputs is stored within the and asserting this pin places the SSRAM in a deep power-down Address Registers and Address Counter/Advancement Logic and mode (SLEEP). White in this mode, Data integrity is guaranteed. then passed or presented to the array core. The corresponding For the device to be placed successfully into this operational data of the addressed location is propagated to the Output mode the device must be deselected and the Chip Enables, ADSP\ Registers and passed to the data bus on the next rising clock via and ADSC\ remain inactive for the duration of tZZREC after the the Output Buffers. The time at which the data is presented to the ZZ input returns LOW. Use of this deep power-down mode Data bus is as specified by either the Clock to Data valid conserves power and is very useful in multiple memory page specification or the Output Enable to Data Valid spec for the designs where the mode recovery time can be hidden. device speed grade chosen. The only exception occurs when the device is recovering from a deselected to select state where its outputs are tristated in the first machine cycle and controlled by its Output Enable (OE\) on following cycle. Consecutive single AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 3 COTS PEM Austin Semiconductor, Inc. Synchronous Truth Tables CE1\ H L L L L L L L X H X H X H X H Notes: 1. X = Don't Care 2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE AS5SP1M18DQ SSRAM Operation Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst, READ Begin Burst, WRITE Begin Burst, READ Continue Burst, READ Continue Burst, READ Continue Burst, WRITE Continue Burst, WRITE Suspend Burst, READ Suspend Burst, READ Suspend Burst, WRITE Suspend Burst, WRITE CE2 X L X L X H H H X X X X X X X X CE3\ X X H X H L L L X X X X X X X X ADSP\ X L L X X L H H H X H X H X H X ADSC\ L X X L L X L L H H H H H H H H ADV X X X X X X X X L L L L H H H H WT / RD X X X X X X WT RD RD RD WT WT RD RD WT WT CLK Address Accessed NA NA NA NA NA External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address Burst Sequence Tables Burst Control Pin [MODE] First Address State HIGH Case 1 A1 0 0 1 1 A0 Interleaved Burst Case 2 A1 A0 0 0 1 0 0 1 1 1 Case 3 A1 1 0 1 0 1 1 0 0 A0 0 1 0 1 A1 1 1 0 0 Case 4 A0 1 0 1 0 Capacitance Parameter Input Capacitance Input/Output Capacitance Clock Input Capacitance Symbol CI CIO CCLK Max. 5.0 5.0 5.0 Units pF pF pF Fourth Address Burst Control Pin [MODE] First Address State LOW Case 1 A1 0 0 1 1 A0 0 1 0 1 Fourth Address Linear Burst Case 2 A1 A0 0 1 1 0 Case 3 A1 1 0 1 0 1 1 0 0 A0 0 1 0 1 A1 Case 4 A0 1 0 0 1 1 0 1 0 Write Table GW\ H H H H H H L BW\ H L L L L L X BWa\ X H L H H L X BWb\ X H H L H L X BWc\ X H H H L L X BWd\ X H H H L L X Operation READ READ WRITE Byte [A] WRITE Byte [B] WRITE Byte [C], [D] WRITE ALL Bytes WRITE ALL Bytes Asynchronous Truth Table Operation Power-Down (SLEEP) READ WRITE De-Selected ZZ H L L L L OE\ X L H X X I/O Status High-Z DQ High-Z Din, High-Z High-Z Absolute Maximum Ratings* Parameter Voltage on VDD Pin Voltage on VDDQ Pins Voltage on Input Pins Voltage on I/O Pins Power Dissipation Storage Temperature Operating Temperatures [Screening Levels] Symbol VDD VDDQ VIN VIO PD tSTG /CT /IT /ET /XT Min. -0.3 VDD -0.3 -0.3 -65 0 -40 -40 -55 VDD+0.3 VDDQ+0.3 1.6 150 70 85 105 125 Max. 4.6 Units V V V V AC Test Loads Output Zo=50 ohm Diagram [A] 30 pF Vt= 1.50v for 3.3v VDDQ Vt= 1.25v for 2.5v VDDQ Rt = 50 ohm W C C C C C Vt= Termination Voltage Rt= Termination Resistor *Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. R= 317 ohm@3.3v R= 1667 ohm@2.5v 3.3/2.5v 5 pF R= 351 ohm@3.3v R= 1538 ohm@2.5v Diagram [B] Output AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 4 COTS PEM Austin Semiconductor, Inc. DC Electrical Characteristics (VDD=3.3v -5%/+10%, TA= Min. and Max temperatures of Screening level chosen) Symbol VDD VDDQ VoH VoL VIH VIL IIL IZZL IOL IDD Parameter Power Supply Voltage I/O Supply Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage (except ZZ) Input Leakage, ZZ pin Output Leakage Operating Current VDD=Max., VIN=VSS to VDD Output Disabled, VOUT=VSSQ to VDDQ VDD=Max., f=Max., IOH=0mA AS5SP1M18DQ SSRAM Test Conditions VDD=Min., IOH=-4mA VDD=Min., IOH=-1mA VDD=Min., IOL=8mA VDD=Min., IOL=1mA 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v Min 3.135 2.375 2.4 2 Max 3.630 VDD 2 1.7 -0.3 -0.3 -5 -30 -5 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz 0.4 0.4 VDD+0.3 VDD+0.3 0.8 0.7 5 30 5 400 350 300 100 90 85 70 80 Units V V V V V V V V V V uA uA uA mA mA mA mA mA mA mA mA Notes 1 1,5 1,4 1,4 1,4 1,4 1,2 1,2 1,2 1,2 3 3 ISB1 Automatic CE. Power-down Current -TTL inputs Max. VDD, Device De-Selected, VIN>/=VIH or VINISB2 ISB4 ISB3 Automatic CE. Power-down Current - CMOS Inputs Automatic CE. Power-down Current -TTL inputs Automatic CE. Power-down Current - CMOS Inputs Max. VDD, Device De-Selected, VIN/=VDDQ-0.3v f=fMAX=1/tCYC Max. VDD, Device De-Selected, VIN>/=VIH or VIN /=VDDQ-0.3v, f-Max=1/tCYC 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz 95 85 80 mA mA mA Thermal Resistance Symbol JA Description Thermal Resistance (Junction to Ambient) Conditions 1-Layer Typical 31 Units 0 Notes 6 C/W JC Test Conditions follow standard test methods and Thermal Resistance procedures for measuring thermal impedance, as (Junction to Top of Case, Top) per EIA/JESD51 6 0 C/W 6 Notes: [1] [2] All Voltages referenced to VSS (Logic Ground) Overshoot: VIH < +4.6V for t [3] [4] [5] [6] AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 5 COTS PEM Austin Semiconductor, Inc. AC Switching Characteristics (VDD=3.3v -5%/+10%, TA= Min. and Max temperatures of Screening level chosen) Parameter Clock (CLK) Cycle Time Clock (CLK) High Time Clock (CLK) Low Time Clock Access Time Clock (CLK) High to Output Low-Z Clock High to Output High-Z Output Enable to Data Valid Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Address Set-up to CLK High Address Hold from CLK High Address Status Set-up to CLK High Address Status Hold from CLK High Address Advance Set-up to CLK High Address Advance Hold from CLK High Chip Enable Set-up to CLK High (CEx\, CE2) Chip Enable Hold from CLK High (CEx\, CE2) Data Set-up to CLK High Data Hold from CLK High Write Set-up to CLK High (GW\, BWE\, BWx\) Write Hold from CLK High (GW\, BWE\, BWX\) ZZ High to Power Down ZZ Low to Power Up Notes to Switching Specifications: 1. 2. 3. 4. 5. 6. 7. 8. Measured as HIGH when above VIH and Low when below VIL This parameter is measured with the output loading shown in AC Test Loads This parameter is sampled Transition is measured +500mV from steady state voltage Critical specification(s) when Design Considerations are being reviewed/analyized for Bus Contentention OE\ is a Don't Care when a Byte or Global Write is sampled LOW A READ cycle is defined by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required SET-UP and HOLD times This is a Synchronous device. All addresses must meet the specified SET-UP and HOLD times for all rising edges of CLK when either ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous inputs must meet the SET-UP and HOLD times with stable logic levels for all rising edges of clock (CLK) during device operation (enabled). Chip Enable (Cex\, CE2) must be valid at each rising edge of clock (CLK) when either ADSP\ or ADSC\ is LOW to remain enabled. Symbol tCYC tCH tCL tCD tCLZ tCHZ tOE tOH tOELZ tOEHZ tAS tAH tASS tASH tADVS tADVH tCES tCEH tDS tDH tWES tWEH tPD tPU -30 [200Mhz] Min. Max. 5.00 2.00 2.00 3.00 1.25 1.25 3.00 3.00 1.25 0.00 3.00 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 2 2 -35 [166Mhz] Min. Max. 6.00 2.20 2.20 3.50 1.25 1.25 3.50 3.50 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 -40 [133Mhz] Min. Max. 7.50 2.50 2.50 4.00 1.25 1.25 3.50 4.00 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycles cycles Notes 1 1 2 2,3,4,5 2,3,4,5 6 2,3,4,5 2,3,4,5 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 AS5SP1M18DQ SSRAM AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 6 COTS PEM Austin Semiconductor, Inc. AC Switching Waveforms Write Cycle Timing AS5SP1M18DQ SSRAM Single Write tCYC tCH Burst Write Pipelined Write CLK tASS tASH tCL ADSP\ ADSP\ Ignored with CE1\ inactive ADSC\ tASS tASH ADV\ tADVS tADVH A2 tAH ADV\ Must be Inactive for ADSP\ Write A3 Ax tAS A1 GW\ tWES tWEH tWES tWEH BWE\, BWx\ tCES tCEH CE1\ Masks ADSP\ CE1\ CE2 CE3\ OE\ DQx,DQPx DON'T CARE UNDEFINED tDS tDH W1 W2a W2b W2c W2d W3 AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 7 COTS PEM Austin Semiconductor, Inc. AC Switching Waveforms Read Cycle Timing AS5SP1M18DQ SSRAM Single Read tCYC tCH Burst Read tCL Pipelined Read CLK tASS tASH ADSP\ Ignored with CE1\ Inactive ADSP\ ADSC\ Initiated Read ADSC\ Suspend Burst ADV\ tADVS tADVH Ax tAS A1 tAH A2 A3 GW\ tWES tWEH BWE\, BWx\ tCES tCEH CE1\ Masks ADSP\ CE1\ Unselected with CE2 CE2 CE3\ OE\ tOE tCD tOEHZ R1 R2a tOH R2b R2c R2d R3a DQx,DQPx DON'T CARE UNDEFINED AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 8 COTS PEM Austin Semiconductor, Inc. AC Switching Waveforms Read/Write Cycle Timing AS5SP1M18DQ SSRAM Pipelined Read Burst Read tCYC tCH tCL CLK tASS tASH ADSP\ ADSC\ ADV\ tADVS tAS tADVH A1R tAH A2W A3W A4R A5R Ax GW\ tWES tWEH BWE\, BWx\ tCES tCEH CE1\ CE2 tCES tCEH CE3\ OE\ tOEHZ tOE tOH A2I A3I A4O [a] A4O [b] A4O [c] A4O [d] DQx,DQPx DON'T CARE UNDEFINED tOELZ A1O tCD AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 9 COTS PEM Austin Semiconductor, Inc. Power Down (SNOOZE MODE) Power Down or Snooze is a Power conservation mode which when building large/very dense arrays, using multiple devices in a multi-banked or paged array, can greatly reduce the Operating current requirements of your total memory array solution. The device is placed in this mode via the use of the ZZ pin, an asynchronous control pin which when asserted, places the array into the lower power or Power Down mode. Awakening the array or leaving the Power Down (SNOOZE) mode is done so by deasserting the ZZ pin . While in the Power Down or Snooze mode, Data integrity is guaranteed. Accesses pending when the device entered the mode are not considered valid nor is the completion of the operation guaranteed. The device must be de-selected prior to entering the Power Down mode, all Chip Enables, ADSP\ and ADSC\ must remain inactive for the duration of ZZ recovery time (tZZREC). AS5SP1M18DQ SSRAM Ordering Information ASI Part Number AS5SP1M18DQ-30IT AS5SP1M18DQ-35IT AS5SP1M18DQ-40IT AS5SP1M18DQ-30ET AS5SP1M18DQ-35ET AS5SP1M18DQ-40ET AS5SP1M18DQ-35XT AS5SP1M18DQ-40XT Configuration 1Mx18, 3.3vCore/3.3,2.5vIO 1Mx18, 3.3vCore/3.3,2.5vIO 1Mx18, 3.3vCore/3.3,2.5vIO 1Mx18, 3.3vCore/3.3,2.5vIO 1Mx18, 3.3vCore/3.3,2.5vIO 1Mx18, 3.3vCore/3.3,2.5vIO 1Mx18, 3.3vCore/3.3,2.5vIO 1Mx18, 3.3vCore/3.3,2.5vIO tCD (ns) 3.0 3.5 4.0 3.0 3.5 4.0 3.5 4.0 Clock (Mhz) 200 166 133 200 166 133 166 133 Industrial Operating Range (-400C to +850C) Enhanced Operating Range (-400C to +1050C) Extended Operating Range (-550C to +1250C) ZZ Mode Electrical Characteristics Parameter Power Down (SNOOZE) Mode ZZ Active (Signal HIGH) to Power Down ZZ Inactive (Signal Low) to Power Up Symbol Test Conditon IDDzz ZZ >/- VDD - 0.2V ZZ >/- VDD - 0.2V tZZS tZZR ZZ 2 tCYC ZZ Mode Timing Diagram Mechanical Diagram 16.00 +/- 0.20mm 14.00 +/- 0.10mm 1.60mm Max. 1.40 +/- 0.05mm CLK ADSP\ 22.00 +/- 0.20mm 0.30 +/- 0.08 ADSC\ CEx\ CE2 20.00 +/- 0.10mm 100 Pin TQFP 14mm x 20mm JEDEC MS026-D/BHA 0.65mm TYP. See Detail A ZZ tZZS tZZREC IDDzz 1.00mm TYP. IDD Detail A 0.10 +0.10/-0.05mm 0.10 Standoff 0.15 MAX 0.05 MIN Seating Plane 12 +/- 1 0.60 +/- 0.15mm AS5SP1M18DQ Revision 1.0 04/04/04 Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com 10 |
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